To increase the computation power of today's computer systems, it is necessary to increase not only the clock frequency of a CPU (Central Processing Unit) but also the speed or bandwidth of system components. Conventionally, fast dynamic read/write memories (DRAM, Dynamic Random-Access Memories) are developed by improving semiconductor technologies, increasing clock rates, etc., which is reflected in the name of the memory systems, such as PC66, PC100, PC133, PC166, . . . etc., or, by way of example, data bus widths are increased by using up to 32 I/Os in the case of SGRAMs for graphics applications.
It is also customary to double a data rate (double data rate, DDR) by using both clock edges, i.e. a rising clock edge and a falling clock edge of the clock signal provided by a clock generator for the purpose of clocking the memory apparatus. In this context, the problem with conventional memory apparatuses is that the DRAMs used need to be synchronized to the frequency of the clock signal—or in the case of DDR methods, to twice the frequency of the clock signal—and need to drive commands, addresses and data streams internally at the same frequency. This disadvantageously results in a high power loss in DRAM chips and in severe stray coupling via driver circuits, internal voltage sources and input/output buffers.
Another inexpediency is that addressing a memory module in a conventional memory module array involves only one memory becoming active. Disadvantageously, it is necessary to provide identification or an identifier or prior decoding for a specific memory module which is to be addressed.
To reduce power consumption in memory apparatuses based on the prior art, the internal supply voltages have been reduced to date, since the power consumption of the memory chip is proportional to the square of these supply voltages. In addition, attempts have been made to reduce the I/O levels or to dissipate an excessive power loss directly by using heat sinks (SGRAM and RAMBUS).
Another drawback of memory apparatuses based on the prior art is that the memory modules driving commands, addresses or data streams internally at the same frequency are sensitive to radio-frequency interference.